The ITER International Fusion Experiment Organization is implementing the real-time framework (RTF) to facilitate the development, deployment, and execution of instrumentation and control (I&C) applications optimized for real-time performance using the GNU/Linux-based ITER CODAC Core System (CCS) software distribution. This contribution examines the feasibility of using hardware acceleration techniques with field-programmable gate arrays (FPGAs) to implement real-time applications in the RTF that requires specific compute intensive functions. By combining the use of languages such as high-level synthesis (HLS) and open computing language (OpenCL) with FPGA devices, specific hardware architectures can be implemented to solve certain computational problems to gain performance and limit latency. This work shows the methodology used to integrate HLS and OpenCL in the ITER CCS and the results obtained in terms of execution time for two common processing operations, vector addition and matrix multiplication, using a commercial off-the-shelf FPGA-based device
The ITER International Fusion Experiment Organization is implementing the real-time framework (RTF) to facilitate the development, deployment, and execution of instrumentation and control (I&C) applications optimized for real-time performance using the GNU/Linux-based ITER CODAC Core System (CCS) software distribution. This contribution examines the feasibility of using hardware acceleration techniques with field-programmable gate arrays (FPGAs) to implement real-time applications in the RTF that requires specific compute intensive functions. By combining the use of languages such as high-level synthesis (HLS) and open computing language (OpenCL) with FPGA devices, specific hardware architectures can be implemented to solve certain computational problems to gain performance and limit latency. This work shows the methodology used to integrate HLS and OpenCL in the ITER CCS and the results obtained in terms of execution time for two common processing operations, vector addition and matrix multiplication, using a commercial off-the-shelf FPGA-based device Read More
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